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ISL97671A
REGISTER 0x0A
PHASE SHIFT CONTROL REGISTER
EQUALPHASE
Bit 7 (R/W)
PHASESHIFT6
Bit 6 (R/W)
PHASESHIFT5
Bit 5 (R/W)
PHASESHIFT4
Bit 4 (R/W)
PHASESHIFT3
Bit 3 (R/W)
PHASESHIFT2
Bit 2 (R/W)
PHASESHIFT1
Bit 1 (R/W)
PHASESHIFT0
Bit 0 (R/W)
BIT ASSIGNMENT
EqualPhase
PhaseShift[6..0]
BIT FIELD DEFINITIONS
Controls phase shift mode - When 0, phase shift is defined by PhaseShift<6:0>. When 1, phase shift
is 360/N (where N is the number of channels enabled).
7-bit Phase shift setting - phase shift between each channel is PhaseShift<6:0>/(255*PWMFreq)
FIGURE 36. DESCRIPTIONS OF PHASE SHIFT CONTROL REGISTER
Phase Shift Control Register (0x0A)
The Phase Shift Control register is used to set phase delay
between channels. When bit 7 is set high, the phase delay is set
by the number of channels enabled and the PWM frequency.
Referring to Figure 3, the delay time is defined by Equation 16:
Input Capacitor
Switching regulators require input capacitors to deliver peak
charging current and to reduce the impedance of the input
supply. The capacitors reduce interaction between the regulator
and input supply, thus improving system stability. The high
t D1 = ( t FPWM ? N )
(EQ. 16)
switching frequency of the loop causes almost all ripple current
to flow into the input capacitor, which must be rated accordingly.
where N is the number of channels enabled, and t FPWM is the
period of the PWM cycle. When bit 7 is set low, the phase delay is
set by bits 6 to 0 and the PWM frequency. Referencing Figure 23,
the programmable delay time is defined by Equation 17:
A capacitor with low internal series resistance should be chosen
to minimize heating effects and to improve system efficiency.
The X5R and X7R ceramic capacitors offer small size and a lower
value for temperature and voltage coefficient compared to other
t PD = ( PS < 6 , 0 > xt FPWM ? ( 255 ) )
(EQ. 17)
ceramic capacitors.
Δ I L = ------- x Δ t
V L
where PS is an integer from 0 to 127, and t FPWM is the period of
the PWM cycle. By default, all the register bits are set low, which
sets zero delay between each channel. Note that the user should
not program the register to have more than one period of the
PWM cycle delay between the first and last enabled channels.
Components Selections
According to the inductor Voltage-Second Balance principle, the
change of inductor current during the switching regulator On
time is equal to the change of inductor current during the
switching regulator Off time. As shown in Equations 18 and 19,
since the voltage across an inductor is:
(EQ. 18)
L
An input capacitor of 10μF is recommended. Ensure that the
voltage rating of the input capacitor is able to handle the full
supply range.
Inductor
Inductor selection should be based on its maximum current (I SAT )
characteristics, power dissipation (DCR), EMI susceptibility
(shielded vs unshielded), and size. Inductor type and value
influence many key parameters, including ripple current, current
limit, efficiency, transient performance, and stability.
Inductor maximum current capability must be adequate to
handle the peak current in the worst-case condition. If an
inductor core with too low a current rating is chosen, saturation
in the core will cause the effective inductor value to fall, leading
to an increase in peak-to-average current level, poor efficiency,
and Δ I L @ On = Δ I L @ Off, therefore:
( V I – 0 ) ? L × D × t S = ( V O – V D – V I ) ? L × ( 1 – D ) × t S
(EQ. 19)
and overheating in the core. The series resistance, DCR, within
the inductor causes conduction loss and heat dissipation. A
shielded inductor is usually more suitable for EMI-susceptible
where D is the switching duty cycle defined by the turn-on time
over the switching period. V D is a Schottky diode forward voltage
that can be neglected for approximation.
Rearranging the terms without accounting for V D gives the boost
ratio and duty cycle, respectively, as shown in Equations 20 and 21:
applications such as LED backlighting.
The peak current can be derived from the voltage across the
inductor during the Off period, as shown in Equation 22:
IL peak = ( V O × I O ) ? ( 85% × V I ) + 1 ? 2 [ V I × ( V O – V I ) ? ( L × V O × f S ) ]
(EQ. 22)
V O ? V I = 1 ? ( 1 – D )
D = ( V O – V I ) ? V O
24
(EQ. 20)
(EQ. 21)
The value of 85% is an average term for the efficiency
approximation. The first term is average current that is inversely
proportional to the input voltage. The second term is inductor
current change that is inversely proportional to L and f S . As a
result, for a given switching frequency and minimum input
voltage at which the system operates, the inductor I SAT must be
chosen carefully.
FN7709.3
November 30, 2012
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